1. Field of the Invention
The present invention relates generally to electrically erasable and programmable non-volatile semiconductor memory devices, and more particularly to an electrically erasable and programmable read only memory having an array of memory cells each of which essentially consists of one transistor. The invention also relates to a redundancy circuitry for use in electrically erasable and programmable non-volatile semiconductor memory devices.
2. Description of the Related Art
Recently, NAND-cell type EEPROMs have been developed as one of highly integrated electrically erasable and programmable read-only memory (EEPROM) devices. With the EEPROMs of this type, an array of rows and columns of memory cells is divided into a plurality of memory cell sections coupled to parallel bit lines on a semiconductor chip substrate. Each cell section includes a predetermined number of series-connected memory cell transistors that are connected in series to one another with each of "middle" semiconductive diffusion layers acting as the source and drain of adjacent ones of the memory cell transistors. Each memory cell transistor may be a floating-gate electron tunneling metal oxide semiconductor (FETMOS) field effect transistor having an insulated gate (floating gate) electrode for storing electrical charge carriers therein and a control gate electrode being coupled to a corresponding word line.
The NAND cell array is arranged either in a P type silicon substrate or in a P type well region formed in an N type silicon substrate. A memory cell transistor positioned at one end of each NAND cell section has a drain coupled to a corresponding bit line through a first switching MOS transistor known as the first "select" transistor. The source of another memory cell transistor that is positioned at the opposite end of the NAND cell section is coupled to a common source voltage (a reference potential wiring line) by way of a second select transistor. The control gate electrodes of NAND cell transistors are connected to one another along the row direction to constitute a plurality of parallel word lines over the substrate.
The operation of the conventional NAND-cell type EEPROM arranged as described above is as follows. A data write for a selected cell section is carried out in such a manner that the memory cell transistors included therein are sequentially subjected to a write operation with a certain memory cell transistor being as a write-starting cell transistor, the certain cell transistor being most distant from the memory cell transistor connected through the first select transistor to a corresponding bit line associated therewith (i.e., the memory cell transistor coupled to the common source potential through the second select transistor). A boosted high voltage Vpp (20 volts, for example) is applied to the control gate of a memory cell transistor being presently selected for write. An intermediate voltage VppM (such as 10 volts), which is a midway potential between a power supply voltage Vcc (5 volts, for example) and the ground potential, is applied to the gate of select transistor (select gate) and the control gate(s) of one or a plurality of non-selected memory cell transistors being positioned between the selected cell transistor and the first select transistor, thereby to render the non-selected cell transistors conductive. A zero-volt voltage or the intermediate voltage VppM is applied to the bit line in accordance with the logic value of a write data.
When the zero-volt voltage is applied to the bit line, a resultant potential thereon is transferred to the drain of the presently selected memory cell transistor through the intervening transistors being rendered conductive. Electrons are thus injected from the drain into the floating gate of the selected cell transistor. The threshold voltage of it is thus shifted positively. The positive shift condition may be defined as a logic "0" storage state. Alternatively, when the intermediate voltage VppM is applied to the bit line, the injection of electrons does not take place, so that the selected cell transistor is kept unchanged in its threshold voltage. This condition may be defined as a logic "1" storage state.
A data erase is carried out so that all the memory cell transistors included in the NAND-cell type EEPROM are erased at a time. More specifically, while the control gates are set at zero volts, (1) the bit lines and the common source line are rendered electrically floating, and (2) the high voltage Vpp is applied to the P type substrate (or both the P type well region and the N type substrate). As a result, electrons accumulated in the floating gates are released or "emitted" to the P type substrate (or to the P type well region) in all the memory cell transistors, causing their threshold voltages to be shifted negatively.
A data read is performed by detecting whether or not a current flows in a selected memory cell transistor while causing the control gate of selected cell transistor to be at zero volts, and applying the power supply voltage Vcc to the control gates of the remaining memory cell transistors and the select gates.
A significant problem of presently-available NAND-cell type EEPROMs is that, unlike the ordinary non-volatile semiconductor memory devices, it is not easy to cure or relieve a defective cell or cells, which are possibly occurred during the manufacturing process of the EEPROMs, by making use of a known redundancy circuitry. More specifically, it is not possible to replace a defective cell array of those memory cells containing a defective cell, which has been found in the final test of the manufacturing process and is coupled to a certain word line, with a corresponding one of subarrays of redundancy cells provided in advance on the same chip substrate by changing an electrical wiring connection therebetween, thereby to cure the defective cell array. The reason for this is described below.
According to presently available NAND-cell type EEPROMs, non-selected memory cell transistors have the specialty that they serve as the "transfer gates" for allowing a data bit to be transferred to or from a target cell transistor as selected during a write period or a read period. Due to such specialty, even if the defective cell subarray is replaced with a redundancy cell subarray with a word line being as a unit, it cannot be expected that a resultant NAND cell block will offer normal operations. Actually, in the art of NAND-cell EEPROMs, although a redundancy circuit scheme for curing defective memory cells has been long desired by the semiconductor manufacturers, nobody hears any successful achievement of such scheme until today. This has been a serious bar to the improvement in the manufacturing yield of the NAND-cell EEPROMs.